Integrated Circuit Fabrication Laboratory

Formerly EE 410. Fabrication, simulation, and testing of a submicron CMOS process. Practical aspects of IC fabrication including silicon wafer cleaning, photolithography, etching, oxidation, diffusion, ion implantation, chemical vapor deposition, physical sputtering, and electrical testing. Students also simulate the CMOS process using process simulator TSUPREM4 of the structures and electrical parameters that should result from the process flow. Taught in the Stanford Nanofabrication Facility (SNF). Preference to students pursuing doctoral research program requiring SNF facilities. Enrollment limited to 20. Prerequisites: EE 212, EE 216, or consent of instructor.